I’m a Senior Embedded Software Engineer at Instituto de Pesquisas Eldorado in Campinas, Brazil, where I’ve worked since 2020 (senior since Nov 2022) on embedded Linux, RTOS, and edge-AI deployment — leading the strategy that took 10+ AI models to production on resource-constrained devices with a 40% inference-latency reduction, alongside MISRA C/C++ compliant firmware and CI/CD for embedded C++ projects.

I’m also a first-year PhD candidate in Electrical Engineering at UFCG, researching multi-UAV formation under intermittent stochastic communication. To be precise about where that stands: the thesis question is multi-UAV formation over a degraded, real communication channel — what’s actually built and working today is a closed-loop trajectory-tracking controller for a single UAV, in simulation. Nothing has flown, and the multi-agent/formation parts aren’t implemented yet. I’d rather say that plainly than let the thesis title imply more than the current artifact.

Before the PhD: an MSc in Electrical and Computer Engineering at UFRN (2020), with a dissertation on embedded artificial neural networks for low-cost, low-memory devices (8-bit MLPs on AVR microcontrollers) — the direct ancestor of the TinyML work I still do today. During the MSc I spent a semester as a Graduate Research Trainee at McGill University, reproducing state-of-the-art neural network results and working on reservoir computing (Echo State Networks) and stochastic computing.

What I actually work with

C/C++, embedded Linux, RTOS (FreeRTOS, Zephyr, NuttX), ARM/STM32, ROS2, sensor fusion and communication protocols (CAN, SPI, I2C, UART, Ethernet), hardware-in-the-loop bench design, and edge-AI model deployment. This site’s Projects page is the concrete version of this list — real repositories, not a bullet list.

Publications

  • Vilar, C. B. & Fernandes, M. A. C. (2020). Real-time Neural Networks Implementation Proposal for Microcontrollers. Electronics, 9(10), 1597. doi.org/10.3390/electronics9101597
  • Vilar, C. B. & Fernandes, M. A. C. (2019). Otimização de Redes Neurais MLP em Microcontroladores de 8 bits Utilizando Memória de Programa. XV Brazilian Congress on Computational Intelligence. doi.org/10.21528/CBIC2019-44
  • Vilar, C. B., Neves, D. & Fernandes, M. A. C. (2018). Proposta de implementação de tempo real de redes neurais MLP em microcontroladores de 8-bits. XIII Brazilian Congress on Computational Intelligence. doi.org/10.21528/cbic2017-106

Elsewhere